1. Field of the Invention
The present invention relates to testing of a nonvolatile memory microcomputer, i.e., a microcomputer with a built-in nonvolatile memory.
2. Related Art
Conventionally, a nonvolatile memory microcomputer which includes a microcomputer unit and a memory unit is tested in the following manner. First, the memory unit is tested using a memory tester. After this, the microcomputer unit is tested using a logic tester. Nonvolatile memory microcomputers which are judged as being nondefective as a result of testing are shipped for use in various products (see Takayanagi, Tajima, & Matsui (ed.) Semiconductor Instrumentation Evaluation Dictionary, First Edition, Science Forum, Feb. 10, 1994, pp. 625–651 as one example).
FIG. 72 shows rough constructions of a conventional nonvolatile memory microcomputer, a memory tester 3400, and a logic tester 3410.
The conventional nonvolatile memory microcomputer is explained first.
In the drawing, the conventional nonvolatile memory microcomputer is roughly made up of a microcomputer unit 3430 and a memory unit 3440. The microcomputer unit 3430 includes circuit blocks such as a CPU 3431, a RAM 3432, a timer 3433, a serial I/F 3434, a port 3435, an A/D converter 3436, and a D/A converter 3437. These circuit blocks are connected to each other by a bus and the like. A signal from outside the microcomputer unit 3430 is supplied to a circuit block via the port 3435. For example, signal S3410 output from the logic tester 3410 to the microcomputer unit 3430 when testing the microcomputer unit 3430 is supplied to a circuit block via the port 3435, to drive that circuit block. Output of a signal from a circuit block in the microcomputer unit 3430 to outside the microcomputer unit 3430 is made via the port 3435, too.
The memory unit 3440 includes a nonvolatile memory 3441 and a memory I/F 3443. The memory I/F 3443 actually sends/receives signals to/from outside the memory unit 3440 via the port 3435, though the memory I/F 3443 is shown to send/receive signals directly to/from outside in FIG. 72 for simplicity's sake.
When a normal operation other than testing is performed, the CPU 3431 in the microcomputer unit 3430 reads/writes data from/to the nonvolatile memory 3441 via the memory I/F 3443.
The memory tester 3400 is explained next.
The memory tester 3400 includes an address generation circuit 3402, a logic comparison circuit 3404, a pass/fail judgment circuit 3405, and a test signal generation circuit 3406.
The test signal generation circuit 3406 outputs control signal S3406a and data S3406b, which are to be supplied to the nonvolatile memory 3441 through the memory I/F 3443. The address generation circuit 3402 outputs address signal S3402, which is to be supplied to the nonvolatile memory 3441 through the memory I/F 3443.
The logic comparison circuit 3404 receives data read from the nonvolatile memory 3441, via the memory I/F 3443. The logic comparison circuit 3404 compares it with predetermined expectation data, and outputs a comparison result to the pass/fail judgment circuit 3405. The pass/fail judgment circuit 3405 judges the memory unit 3440 as being defective, if the comparison result indicates a mismatch. Otherwise, the pass/fail judgment circuit 3405 judges the memory unit 3440 as being nondefective. The pass/fail judgment circuit 3405 informs a user of the memory tester 3400 of a judgment result, by means of display or the like.
The memory unit 3440 is tested with the microcomputer unit 3430 being put in a reset state and the port 3435 in the microcomputer unit 3430 being put in a memory test state. The memory test state referred to here is a state where the memory tester 3400 and the memory unit 3440 are substantially directly connected. This being so, the test signal generation circuit 3406 supplies a read control signal, or a write control signal and write data, to the memory I/F 3443. Meanwhile, the address generation circuit 3402 supplies an address signal to the memory I/F 3443. This causes the nonvolatile memory 3441 to operate. The logic comparison circuit 3404 checks an operation result of the nonvolatile memory 3441. In FIG. 72, boxed numbers 1 to 7 indicate signal flows when the memory unit 3440 is tested.
The logic tester 3410 is explained next.
The logic tester 3410 includes a pattern generator 3411, a waveform shaping circuit 3412, a timing generator 3413, an input signal reference voltage generator 3414, an I/O signal control circuit 3415, a comparison reference voltage generator 3416, a logic comparison circuit 3417, a pass/fail judgment circuit 3418, and a defect analysis memory 3419.
The pattern generator 3411 generates a test pattern showing an instruction to be given to the microcomputer unit 3430, and sends it to the waveform shaping circuit 3412 as test pattern S3411a. The pattern generator 3411 also generates an expectation pattern showing a test result which is expected when the microcomputer unit 3430 operates correctly, and sends it to the logic comparison circuit 3417 as expectation pattern 3411b. 
The waveform shaping circuit 3412 receives test pattern S3411a from the pattern generator 3411, and shapes test pattern S3411a into a signal waveform most suitable for testing, under control of the timing generator 3413. The waveform shaping circuit 3412 sends the signal waveform to the I/O signal control circuit 3415.
The I/O signal control circuit 3415 receives the signal waveform from the waveform shaping circuit 3412, and converts it into a high level or a low level that are determined by an input signal reference voltage generated from the input signal reference voltage generator 3414. The I/O signal control circuit 3415 outputs resulting signal S3410 to the nonvolatile memory microcomputer, to drive a circuit block in the microcomputer unit 3430. The circuit block in the microcomputer unit 3430 operates according to signal S3410, and returns signal S3430 showing an operation result to the I/O signal control circuit 3415.
The I/O signal control circuit 3415 receives signal S3430, and converts it into a high level or a low level that are determined by a comparison reference voltage generated from the comparison reference voltage generator 3416. The I/O signal control circuit 3415 outputs resulting data S3415a and S3415b to the logic comparison circuit 3417.
The logic comparison circuit 3417 compares data S3415a and S3415b with expectation pattern S3411b. If they match, the logic comparison circuit 3417 sends a pass signal indicating that the nonvolatile memory microcomputer is nondefective, to the pass/fail judgment circuit 3418 and the defect analysis memory 3419. If they do not match, the logic comparison circuit 3417 sends a fail signal indicating that the nonvolatile memory microcomputer is defective, to the pass/fail judgment circuit 3418 and the defect analysis memory 3419.
The defect analysis memory 3419 stores, upon receiving the fail signal from the logic comparison circuit 3417, test pattern identification data S3411c which is output from the pattern generator 3411 in sync with test pattern S3411a. As a result, defects can be identified by referring to the defect analysis memory 3419.
The microcomputer unit 3430 is tested with connector terminals of the logic tester 3410 being connected to signal I/O terminals of the nonvolatile memory microcomputer. This being so, the logic tester 3410 outputs signal S3410 for driving the microcomputer unit 3430, to the port 3435. The logic tester 3410 then receives signal S3430 showing a driving result from the port 3435, and judges whether signal S3430 matches an expected result. Usually, the testing is performed using a lot of test patterns. In FIG. 72, circled numbers 1 and 2 indicate signal flows when the microcomputer unit 3430 is tested.
Thus, conventionally a nonvolatile memory microcomputer is tested in two steps, that is, a step of testing a memory unit using a memory tester and a step of testing a microcomputer unit using a logic tester.
To shorten testing time, the following method is typically employed. A test device which functions as a plurality of memory testers is connected with a plurality of nonvolatile memory microcomputer chips, to test a memory unit of each nonvolatile memory microcomputer chip in parallel. Also, a test device which functions as a plurality of logic testers is connected with a plurality of nonvolatile memory microcomputer chips, to test a microcomputer unit of each nonvolatile memory microcomputer chip in parallel.
However, since the number of terminals equipped in one test device is limited, only a limited number of nonvolatile memory microcomputer chips can be tested in parallel. In general, more connector terminals are needed to test a microcomputer unit than to test a memory unit. Therefore, particularly when testing a microcomputer unit, only a small number of nonvolatile memory microcomputer chips can be tested in parallel.
Furthermore, an operation of testing a memory unit using a memory tester in one step and testing a microcomputer unit using a logic tester in another step requires changes to be made on connection and the like between the two steps. This causes a decrease in testing efficiency.